New Features of Intels Next Generation ProcessorPoulson

Image source: http://assets.hardwarezone.com/img/2015/09/skylake-desktop-capability_1.jpg

At last week's Hot Chips conference in California, Intel released the updated architecture features of its upcoming Itanium processor with the codename as Poulson. The new architecture features include Instruction Replay, improved Hyper-Threading and new instructions and so on, aiming to use the next-generation 12-wide release architecture.

The Instruction Replay technology is one of the new features, which could make the wrong instruction re-execute, and then automatically cover the serious mistakes and further help to prevent the system collapse and data damage. Additionally, this Instruction Replay technology is an important remote access services update and the first Intel chip to have the capability.

General Manager at Intel's Data Center Group, Pauline Nist said, utilizes a new pipeline architecture to expand error detection in order to capture transient errors in execution. Upon error detection, instructions can then be re-executed from the instruction buffer queue to automatically recover from severe errors to improve resiliency.

Besides these, for almost all main architectures in the Itanium core design, Poulson adds extensive RAS (reliability, availability and serviceability) protections, including LLC (last level cache), MLI (mid-level instruction cache), MLD (mid-level data cache), IEU (integer execution unit) and FPU (floating-point unit), etc.

This technology enables the second feature, improved Hyper-Threading which brings better performance and support for Dual Domain Multithreading. This allows for front and backend pipeline execution, therefore improving Poulson's parallelism.

Moreover, Intel is adding instructions in four areas as well. There are new integer operations, expanded data access hints, expanded software prefetch and thread control. It is worthwhile for Xeon customers to keep an eye on Itanium updates and features because they are likely to appear in future Xeon CPUs.

The new Itanium instructions of Intel simplify unified task and branch operations to help the future Itanium to promote into the next level.

Key points of Poulson:

Eight high capacity core
54MB memory chips (50MB of an SRAM)
Adopting 32 nm made 3.1 billion transistors
The higher, the bus speed (QPI and SMI) will increase 33% system bandwidth
The next generation of architecture improves the new data and instructions channel, floating point channel and instruction cache.
Improve the power management function, reduce the socket power consumption.
Compatible with the present Intel Itanium 9300 electronic components processor series.
Intel announced that Poulson Itanium electronic component processor is the most advanced Intel processor so far which is about to launch in 2012. The next-generation Itanium processor followed Poulson is code-named as Kittson which is being developed and would be released in 2014.